搜索资源列表
I2CSLAVE
- 已经验证过的I2C，slave的IP，core，从一开源网站下载的，代码写的非常好，节省了FPGA的资源，比起以往的slave的CORE，这个CORE减少了寄存器的使用。-Has been verified I2C, slave of the IP, core, from an open source website, the code is written in a very good save FPGA resources than the previous slave of CORE, t
DW8051
- 8051Ip核内部ram。很多8051iP核都没有内部ram，上传一个希望对大家有用-internel ram of 8051Ip
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
ac97_latest.tar
- simple AC97 Controller IP core. It supports one AC97 codec, with 6 output and 3 input channels. This AC97 Controller s fully AC97 Revision 2.2 compliant. it only supports AC97 Audio Codecs.
C8051_mega_core.tar
- 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
8051code
- VHDL源码 8051+IP内核 在xilinx环境仿真运行 不带接口的逻辑部分代码-VHDL source code 8051+ IP cores in the xilinx environment simulation to run without a logical part of the code interface
i2c
- i2c master controller, free ip
eth_ocm_80_3
- MAC ethernet ip opencore
arm7verilog
- ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
FPGA_SOPC_PWM
- 将此文件解压缩，会得到一个"ip"目录，将此目录放入你的项目中，就可以在sopc中import到一个叫pwm的组建了。解压缩还会得到一个C语言文件，它是与硬件配合的Nios2_C代码 -Extract this file will get an " ip" directory into this directory in your project, you can import into the sopc in the formation of a called pwm.
12130_ARM_Core
- arm 核，VHDL语言描述的IP软核，仅供学习-arm-core, VHDL language to describe the IP soft core, only to learn
8051_latest
- 8051ip核，可用于ic设计和FPGA的软ip核使用-8051ip nuclear, can be used for ic design and FPGA soft-core use of ip
UP_IP_Library_80
- altera大学IP库，包含ps2、sdram、rs232等-altera University, IP libraries, including the ps2, sdram, rs232, etc.
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
FPGA_RS232
- 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous ser
C8255
- 这是ALDEC公司的8255IP core，是用VHDL 语言写的，包括文档和代码-This is a ALDEC the company' s 8255IP core, is written in VHDL language, including the documentation and code
Usb_ISP1362
- 飞利浦公司Usb芯片ISP1362在nios中的IP核，可以用-Philips Usb-chip ISP1362 in nios in the IP core, you can use
IPcore
- 十五个IP核。。。比较常用的，大家可以参考-failed to translate
sd_slave_device
- verilog source code for SD card SLAVE DEVICE IP-Core
cordic
- altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.